Method of manufacturing semiconductor device

ABSTRACT

Disclosed herein is a method for manufacturing a semiconductor device, the method including the steps of: forming a recess in an insulating film provided over a substrate; forming a plating seed layer in such a way that an inner wall of the recess is covered, the plating seed layer arising from sequential deposition of an alloy layer composed of copper and a metal other than copper and a conductive layer composed mainly of copper; burying a conductive layer composed mainly of copper by plating in the recess on which the plating seed layer is provided; and carrying out heat treatment to cause the metal in the alloy layer to react with a constituent in the insulating film, to thereby form a barrier film composed of a metal compound having a copper diffusion barrier function at an interface between the alloy layer and the insulating film.

CROSS REFERENCES TO RELATED APPLICATIONS

The present invention contains subject matter related to Japanese Patent Application JP 2006-222194 filed in the Japan Patent Office on Aug. 17, 2006, the entire contents of which being incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device that has a damascene structure in which a self-formed barrier film is provided between an interconnect or via and an interlayer insulating film.

2. Description of the Related Art

In a general process for forming a copper (Cu) interconnect in a semiconductor device, a damascene method is employed, in which an interconnect pattern is formed by filling an interconnect trench provided in an interlayer insulating film. In formation of a Cu interconnect by use of the damascene method, generally before burying of Cu, a barrier film such as a tantalum (Ta) or tantalum nitride (TaN) film is deposited to a film thickness of about 10 nm in such a manner as to cover the inner wall of an interconnect trench, for the purpose of preventing diffusion of Cu into an interlayer insulating film. After the deposition of the barrier film, by electrolytic plating, a Cu layer is buried in the interconnect trench on which the barrier film is provided.

However, as the interconnect pitch becomes smaller, the burying of Cu becomes more difficult. In addition, the volume ratio of the barrier film to the total interconnect volume becomes higher, which increases the interconnect resistance. To address these problems, a countermeasure technique has been proposed (refer to e.g. “Low Resistive and Highly Reliable Cu Dual-Damascene Interconnect Technology Using Self-Formed MnSixOy Barrier Layer”, 2005 IEEE International Interconnect Technology Conference, pp. 188 to 190). In this technique, a barrier film is not deposited but a seed layer formed of a Cu layer containing Mn is formed. Furthermore, Mn is diffused through heat treatment to thereby form a self-formed barrier film composed of a Mn compound and having a film thickness of about 2 to 3 nm at the interface between an interlayer insulating film and a Cu interconnect.

This self-formed barrier process will be described below with reference to FIG. 3A to 3C. Referring initially to FIG. 3A, an interlayer insulating film 12 composed of silicon oxide (SiO₂) is formed on a substrate 11 formed of a silicon wafer. Thereafter, a via hole 13 reaching the substrate 11 is formed in the interlayer insulating film 12, and then a via 14 composed of e.g. tungsten (W) is buried in the via hole 13.

Subsequently, an interlayer insulating film 15 composed of SiO₂ is formed on the interlayer insulating film 12 and the via 14. Subsequently, in the interlayer insulating film 15, an interconnect trench 16 reaching the interlayer insulating film 12 and the via 14 is formed. Thereafter, on the interlayer insulating film 15, a plating seed layer 17′ formed of a CuMn layer is formed.

Referring next to FIG. 3B, by electrolytic plating, a conductive layer 18 composed of pure Cu is formed on the plating seed layer 17′ in such a manner as to fill the interconnect trench 16.

Referring next to FIG. 3C, heat treatment is carried out to cause Mn contained in the plating seed layer 17′ to react with a constituent in the interlayer insulating films 12 and 15, to thereby form a self-formed barrier film 19 composed of a Mn compound at the interfaces between the plating seed layer 17′ and the interlayer insulating films 12 and 15. This self-formed barrier film 19 is formed to have a film thickness of 2 nm to 3 nm. Through the heat treatment, Mn is segregated also on the surface side of the conductive layer 18, so that a manganese oxide (MnO) layer M is formed.

Thereafter, although not shown in the drawing, by chemical mechanical polishing (CMP), the part of the conductive layer 18 and the self-formed barrier film 19 unnecessary as an interconnect pattern is removed and the surface side of the exposed interlayer insulating film 15 is polished down, so that an interconnect is formed in the interconnect trench 16.

The above-described manufacturing method is superior to a typical burying process employing a Ta or TaN barrier film in provision of good coverage of a conductive layer 18, because the self-formed barrier film 19 with a smaller thickness is formed through reaction of Mn in the plating seed layer 17′ with a constituent in the interlayer insulating films 12 and 15. Furthermore, this manufacturing method further provides an advantage of achieving an interconnect with lower resistance, because the film thickness of the self-formed barrier film 19 is smaller than that of the Ta or TaN barrier film.

SUMMARY OF THE INVENTION

However, the above-described manufacturing method involves the following problems. Specifically, if the concentration of Mn in the plating seed layer 17′ is insufficient, the step described with FIG. 3C will fail to form the continuous self-formed barrier film 19 as shown in FIG. 4. This will result in separation of the conductive layer 18 due to the lowering of the adhesiveness between the conductive layer 18 and the interlayer insulating films 12 and 15 attributed to a sharp stress change at the initial stage of the heat treatment. To prevent this, it would be effective to increase the concentration of Mn in the plating seed layer 17′ (see FIG. 3C) for promotion of the formation of the self-formed barrier film 19. However, because Mn is higher than Cu in the resistance, the increase in the Mn concentration yields higher sheet resistance of the plating seed layer 17′. This leads to the necessity for application of a large current in the plating step, and thus increases the burden on the plating step. This causes unevenness of the plating growth of the conductive layer 18 across the plane of the substrate 11, which results in low uniformity of the coverage of the conductive layer 18. Moreover, Mn on the surface side of the plating seed layer 17′ is easily eluted in a plating solution, which leads to a problem that the Mn eluted in the plating solution is buried in the interconnect trench 16 together with the conductive layer 18 and hence the interconnect resistance increases.

There is a need for the present invention to provide a method for manufacturing a semiconductor device, allowing prevention of separation of a conductive layer while suppressing the burden on a plating step, and allowing enhancement in the uniformity of the coverage of the conductive layer across the substrate plane while suppressing increase in the interconnect resistance.

In a method for manufacturing a semiconductor device according to an embodiment of the present invention, the following steps are sequentially carried out. Initially, a recess is formed in an insulating film provided over a substrate. Subsequently, a plating seed layer arising from sequential deposition of an alloy layer composed of copper (Cu) and a metal other than Cu and a conductive layer composed mainly of Cu is formed in such a way that the inner wall of the recess is covered. Next, by plating, a conductive layer composed mainly of Cu is buried in the recess on which the plating seed layer is provided. Subsequently, heat treatment is carried out to cause the metal in the alloy layer to react with a constituent in the insulating film, to thereby form a barrier film composed of a metal compound having a Cu diffusion barrier function at the interface between the alloy layer and the insulating film.

According to such a method for manufacturing a semiconductor device, even when the resistance of the metal other than Cu contained in the alloy layer is high, the sheet resistance of the plating seed layer is lower than that of a plating seed layer formed only of the alloy layer, because the plating seed layer arising from sequential deposition of the alloy layer and the conductive layer composed mainly of Cu is formed. Therefore, even when the concentration of the metal in the alloy layer is increased to such an extent that a continuous barrier film is formed, increase in the sheet resistance of the plating seed layer is suppressed. This eliminates the need to apply a large current in a plating step, and thus suppresses the burden on the plating step. Thus, with the burden on the plating step suppressed, a continuous barrier film can be formed at the interface between the alloy layer and the insulating film by increasing the concentration of the metal in the alloy layer. This enhances the adhesiveness between the conductive layer and the insulating film, which can prevent separation of the conductive layer. In addition, due to the low sheet resistance of the plating seed layer, unevenness of the plating growth of the conductive layer across the substrate plane is suppressed and the uniformity of the coverage of the conductive layer is enhanced. Moreover, because the alloy layer in the plating seed layer is covered by the conductive layer composed mainly of Cu, the metal on the surface side of the alloy metal is prevented from being eluted in a plating solution in the plating step. This prevents increase in the resistance of the conductive layer due to burying of the metal eluted in the plating solution in the recess together with the conductive layer at the time of filling of the recess with the conductive layer by plating.

As described above, the method for manufacturing a semiconductor device according to an embodiment of the present invention can prevent separation of a conductive layer, and thus can enhance the yield of the semiconductor device. Furthermore, the uniformity of the coverage of the conductive layer across the substrate plane is enhanced, which can suppress dishing and erosion that will occur in polishing of the conductive layer by e.g. CMP. Moreover, increase in the resistance of the conductive layer can be prevented. Consequently, when the recess is an interconnect trench and the conductive layer is an interconnect, increase in the interconnect resistance can be prevented and the interconnect reliability can be enhanced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1F are sectional views for explaining manufacturing steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

FIGS. 2A to 2K are sectional views for explaining manufacturing steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention;

FIGS. 3A to 3C are sectional views for explaining manufacturing steps of an existing method for manufacturing a semiconductor device; and

FIG. 4 is a sectional view for explaining a problem relating to the existing method for manufacturing a semiconductor device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be described in detail below with reference to the drawings.

First Embodiment

A method for manufacturing a semiconductor device according to a first embodiment of the present invention relates to formation of a single damascene interconnect structure. The first embodiment will be described below with reference to FIGS. 1A to 1F as sectional views of manufacturing steps. In the following description, the same components as those in the related art are given the same numerals.

Referring initially to FIG. 1A, an interlayer insulating film 12 composed of e.g. SiO₂ is formed on a substrate 11 formed of a silicon wafer on which elements such as transistors are formed. Thereafter, a via hole 13 reaching the substrate 11 is formed, and then a via 14 composed of e.g. W is buried in the via hole 13.

Subsequently, by e.g. plasma enhanced chemical vapor deposition (PECVD) with use of silane (SiH₄) as the deposition gas, an interlayer insulating film 15 composed of e.g. SiO₂ is formed on the interlayer insulating film 12 and the via 14.

Subsequently, a resist pattern (not shown) having an interconnect trench pattern is formed on the interlayer insulating film 15, and then an interconnect trench 16 (recess) is formed in the interlayer insulating film 15 by etching with use of this resist pattern as the mask. The aperture width of this interconnect trench 16 is 75 nm.

Referring next to FIG. 1B, by e.g. physical vapor deposition (PVD) such as sputtering with use of a CuMn alloy target, an alloy layer 17 a composed of CuMn is formed on the interlayer insulating film 15 in such a manner as to cover the inner wall of the interconnect trench 16. The resistance of Mn is higher than that of Cu. Furthermore, by heat treatment in a later step, Mn in the alloy layer 17 a reacts with a constituent in the interlayer insulating films 12 and 15 to thereby form a self-formed barrier film.

Therefore, the concentration of Mn in the alloy layer 17 a and the film thickness of the alloy layer 17 a are defined within certain ranges. Specifically, the values of the Mn concentration and the film thickness are equal to or larger than the lower limits for formation of a continuous self-formed barrier film at the interfaces between the alloy layer 17 a and the interlayer insulating films 12 and 15 through heat treatment in a later step. In addition, the values of the Mn concentration and the film thickness are equal to or smaller than the upper limits that yield the allowable upper limits of the interconnect resistance of an interconnect formed in the interconnect trench 16 and containing remaining Mn and the sheet resistance of a plating seed layer arising from stacking of a conductive layer composed mainly of Cu, to be described later, on the alloy layer 17 a.

Specifically, the Mn concentration in the alloy layer 17 a is in the range of 1 atomic % to 10 atomic %, and it is preferable that the Mn concentration be in the range of 2 atomic % to 6 atomic %. Furthermore, the film thickness of the alloy layer 17 a is defined to be not larger than a certain value so that the quality of filling with a conductive layer by later plating may not be deteriorated as well as to be at most the above-described upper limit. Specifically, the film thickness of the alloy layer 17 a is in the range of 10 nm to 50 nm in a smooth part having no interconnect trench pattern. In the present example, the alloy layer 17 a is formed to have a film thickness of e.g. 30 nm.

Referring next to FIG. 1C, on the alloy layer 17 a, a conductive layer 17 b composed of e.g. pure Cu is formed to a film thickness of e.g. 30 nm. This forms a plating seed layer 17 arising from the sequential deposition of the alloy layer 17 a and the conductive layer 17 b in that order. This allows the surface side of the alloy layer 17 a to be covered by the conductive layer 17 b composed of pure Cu. Therefore, the plating seed layer 17 has lower sheet resistance compared with a plating seed layer formed only of the alloy layer 17 a composed of CuMn. This suppresses the burden on a plating step for burying a conductive layer in the interconnect trench 16 to be described later.

In the present example, the conductive layer 17 b is composed of pure Cu. However, the material of the conductive layer 17 b may be any as long as it contains Cu as its main constituent. For example, a CuAg alloy, which yields small resistivity increase, may be used.

The film thickness of the conductive layer 17 b is so set that the sheet resistance of the plating seed layer 17 is suppressed within the allowable range and the quality of filling with a conductive layer 18 by plating is not deteriorated as described above. Specifically, the film thickness of the conductive layer 17 b is in the range of 10 nm to 50 nm in a smooth part having no interconnect trench pattern. In the present example, the conductive layer 17 b is formed to have a film thickness of e.g. 30 nm.

Referring next to FIG. 1D, by e.g. electrolytic plating, the conductive layer 18 composed of e.g. pure Cu is formed on the conductive layer 17 b to a film thickness of 800 nm or more in such a manner as to fill the interconnect trench 16. In this burying, the uniformity of the coverage of the conductive layer 18 across the plane of the substrate 11 is high because the sheet resistance of the plating seed layer 17 is low as described above. Moreover, the surface side of the alloy layer 17 a is covered by the conductive layer 17 b composed of pure Cu. This prevents Mn on the surface side of the alloy layer 17 a from being eluted in the plating solution, and thus prevents burying of Mn eluted in the plating solution in the interconnect trench 16 together with the conductive layer 18. Thus, increase in the interconnect resistance is prevented. Moreover, adverse effects on the plating step due to Mn eluted in the plating solution are avoided.

In the present example, the conductive layer 18 is composed of pure Cu. However, the material of the conductive layer 18 may be any as long as it contains Cu as its main constituent. For example, a CuAg alloy, which yields small resistivity increase, may be used.

Referring next to FIG. 1E, heat treatment at 300° C. for 30 minutes is carried out for example. This heat treatment causes Mn in the alloy layer 17 a (see FIG. 1D) to react with a constituent in the interlayer insulating films 12 and 15, to thereby form a self-formed barrier film 19 having a function to prevent Cu diffusion at the interfaces between the alloy layer 17 a and the interlayer insulating films 12 and 15. It is preferable that the temperature and treatment time of the heat treatment for forming the self-formed barrier film 19 be 200° C. to 400° C. and 60 seconds to two hours, respectively, in order to promote assured formation of the self-formed barrier film 19 and prevent adverse effects on the device due to the heat treatment. It is more preferable that the treatment time be 60 seconds to 30 minutes. The “constituent” in the interlayer insulating films 12 and 15 encompasses also oxygen, water, and so on that are absorbed by the surfaces of the interlayer insulating films 12 and 15 from the atmosphere.

In the present embodiment, the interlayer insulating films 12 and 15 are composed of SiO₂, and therefore the self-formed barrier film 19 is composed of a Mn compound such as a silicon-containing Mn oxide (MnSi_(x)O_(y)) or Mn oxide (Mn_(x)O_(y)). The film thickness of the self-formed barrier film 19 is 2 nm to 3 nm. The alloy layer 17 a contains Mn with such a high concentration that the continuous self-formed barrier film 19 is formed. This permits a larger amount of Mn to be supplied to the interfaces between the alloy layer 17 a and the interlayer insulating films 12 and 15 compared with an existing method, which allows formation of the continuous self-formed barrier film 19 that is robust and offers high adhesiveness. This prevents the occurrence of separation of the conductive layer 18 due to a sharp stress change at the initial stage of the heat treatment. Furthermore, a wide margin can be assured for the condition of the heat treatment. Due to this heat treatment, Mn is segregated also on the surface side of the conductive layer 18, which forms a MnO layer M.

Referring next to FIG. 1F, two-stage polishing is carried out by e.g. CMP. In the first-stage polishing, the MnO layer M (see FIG. 1E) and the part of the conductive layer 18 (see FIG. 1E) unnecessary as an interconnect pattern are removed. Subsequently, in the second-stage polishing, the self-formed barrier film 19 is removed, and the exposed interlayer insulating film 15 is polished down by 100 nm. This forms an interconnect 18′ composed of Cu in the interconnect trench 16. Because the above-described self-formed barrier film 19 is provided at the interfaces between the conductive layer 18 and the interlayer insulating films 12 and 15, separation of the conductive layer 18 due to the CMP step is prevented, and thus a wide margin can be assured for the condition of the CMP.

Subsequently to the CMP step, an organic acid cleaning is carried out with use of a citric acid aqueous solution, oxalic acid aqueous solution, and so on, to thereby remove an oxide film on the interconnect 18′ and an anticorrosive agent for Cu, such as a benzotriazole derivative, remaining on the Cu surface after the CMP step. Thereafter, a cap film 20 composed of e.g. silicon carbonitride (SiCN) is deposited to a film thickness of 50 nm on the interconnect 18′ and the interlayer insulating film 15 by CVD with use of a silicon-containing material such as trimethylsilane (3MS), ammonia (NH₃), and so on as the deposition gas.

In the above-described method for manufacturing a semiconductor device, the plating seed layer 17 arising from sequential deposition of the alloy layer 17 a and the conductive layer 17 b composed of pure Cu is formed as described with FIG. 1C. This can provide increased concentration of Mn in the alloy layer 17 a while suppressing the burden on a plating step. Thus, the continuous self-formed barrier film 19 can be formed at the interfaces between the alloy layer 17 a and the interlayer insulating films 12 and 15. This enhances the adhesiveness between the conductive layer 18 and the interlayer insulating films 12 and 15, which can prevent separation of the conductive layer 18. Consequently, the yield of the semiconductor device can be enhanced. Furthermore, wide margins can be assured for the condition of the heat treatment for forming the self-formed barrier film 19 and the condition of the CMP for polishing the conductive layer 18.

In addition, the sheet resistance of the plating seed layer 17 can be set lower, which can enhance the uniformity of the coverage of the conductive layer 18 across the plane of the substrate 11. Therefore, dishing and erosion in the polishing of the conductive layer 18 by CMP can be suppressed, which can enhance the interconnect reliability.

Moreover, because the alloy layer 17 a is covered by the conductive layer 17 b composed of pure Cu, eluting of Mn in a plating solution in the plating step is prevented. This can prevent increase in the resistance of the interconnect 18′ due to burying of Mn in the interconnect trench 16 together with the conductive layer 18.

Table 1 shows the result of comparison among the sheet resistance values of a plating seed layer (1), to which a method for manufacturing a semiconductor device according to an embodiment of the present invention is applied, and plating seed layers (2) and (3), to which an embodiment of the present invention is not applied.

TABLE 1 Sheet Configuration (Film Resistance Thickness) (Ω/□) Plating Seed Pure Cu Layer (30 nm)/ 1.027 Layer (1) 2-A %-Mn-containing CuMn Layer (30 nm) Plating Seed 2-A %-Mn-containing CuMn Layer 3.277 Layer (2) (60 nm) Plating Seed A %-Mn-containing CuMn Layer 1.873 Layer (3) (60 nm)

The plating seed layer (1) is obtained by depositing a pure Cu layer (conductive layer 17 b) having a film thickness of 30 nm on a 2-A %-Mn-containing CuMn layer (alloy layer 17 a) having a film thickness of 30 nm. The plating seed layer (2) is formed of a 2-A %-Mn-containing CuMn layer having a film thickness of 60 nm. As shown in this table, it is confirmed that the sheet resistance of the plating seed layer (1) is greatly lower than that of the plating seed layer (2). The plating seed layer (3) is formed of a A %-Mn-containing CuMn layer having a film thickness of 60 nm, and therefore has the Mn concentration half that of the plating seed layer (2). As shown in the table, it is confirmed that the sheet resistance of the plating sheet layer (1) is lower than that of the plating seed layer (3) although the total Mn concentration of the plating seed layer (3) is equivalent to that of the plating seed layer (1). Consequently, it is confirmed that the sheet resistance of the plating seed layer 17 is greatly decreased through deposition of the conductive layer 17 b composed of pure Cu on the alloy layer 17 a composed of CuMn compared with the case where the plating seed layer 17 is formed only of the alloy layer 17 a.

Second Embodiment

A method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described below with reference to FIGS. 2A to 2K as sectional views of manufacturing steps. For the description of the method according to the second embodiment, an example in which a dual damascene interconnect structure is formed over the cap film described in the first embodiment will be described.

Referring initially to FIG. 2A, on the cap film 20, an interlayer insulating film 21 composed of e.g. SiO₂ is deposited to a film thickness of 350 nm by e.g. PE-CVD. Subsequently, a resist pattern (not shown) having a via hole pattern is formed on the interlayer insulating film 21, and then a via hole 22 a reaching the cap film 20 is formed by etching with use of this resist pattern as the mask.

Referring next to FIG. 2B, a resist R is applied on the interlayer insulating film 21 in such a manner as to fill the via hole 22 a. Subsequently, a spin-on-glass (SOG) film is formed on the resist R, and then a resist pattern (not shown) having an interconnect trench pattern is formed on the SOG film. Thereafter, the SOG film is processed by etching with use of this resist pattern as the mask, so that a hard mask 23 is formed.

Referring next to FIG. 2C, the resist R (see FIG. 2B) is processed by etching with use of the hard mask 23 as the etching mask, to thereby form a resist pattern R′ having an interconnect trench pattern. The resist R covering the bottom of the via hole 22 a is left.

Referring next to FIG. 2D, by etching with use of the hard mask 23 (see FIG. 2C) and the resist pattern R′ as the etching mask, an interconnect trench 22 b in communication with the via hole 22 a is formed in the upper side of the interlayer insulating film 21. This forms a dual damascene aperture 22 (recess) composed of the interconnect trench 22 b and the via hole 22 a in communication with the bottom of the interconnect trench 22 b. The depth of the interconnect trench 22 b is controlled through control of the etching time. The aperture width and depth of the via hole 22 a are 75 nm and 110 nm, respectively. The aperture width and depth of the interconnect trench 22 b are 75 to 100 nm and 150 nm, respectively. Because the resist R is left inside the via hole 22 a, etching of the sidewall of the via hole 22 a is prevented, and thus the sidewall is kept vertical.

Referring next to FIG. 4E, the resist pattern R′ (see FIG. 2D) and the resist R (see FIG. 2D) are removed by ashing and chemical cleaning, so that the cap film 20 at the bottom of the via hole 22 a is exposed.

Subsequently, as shown in FIG. 2F, the cap film 20 at the bottom of the via hole 22 a is removed to thereby expose the surface of the interconnect 18′.

Referring next to FIG. 2G, by e.g. sputtering, an alloy layer 24 a composed of a CuMn alloy is so formed on the interlayer insulating film 21 that the inner wall of the dual damascene aperture 22 is covered. Similarly to the first embodiment, the Mn concentration in this alloy layer 24 a is in the range of 1 atomic % to 10 atomic %, and it is preferable that the Mn concentration be in the range of 2 atomic % to 6 atomic %. The film thickness of the alloy layer 24 a is in the range of 10 nm to 50 nm in a smooth part having no interconnect trench pattern.

Referring next to FIG. 2H, a conductive layer 24 b composed of e.g. pure Cu is formed on the alloy layer 24 a. This forms a plating seed layer 24 arising from sequential deposition of the alloy layer 24 a and the conductive layer 24 b. Similarly to the first embodiment, the film thickness of this conductive layer 24 b is in the range of 10 nm to 50 nm in a smooth part having no interconnect trench pattern.

Referring next to FIG. 2I, a conductive layer 25 composed of e.g. pure Cu is formed on the Cu layer 24 b in such a manner as to fill the dual damascene aperture 22.

Referring next to FIG. 2J, heat treatment at 300° C. for 30 minutes is carried out for example. This heat treatment causes Mn in the alloy layer 24 a (see FIG. 2I) to react with a constituent in the interlayer insulating film 21, to thereby form a self-formed barrier film 26 composed of a Mn compound with a function to prevent Cu diffusion between the alloy layer 24 a and the interlayer insulating film 21. Similarly to the first embodiment, the interlayer insulating film 21 is composed of SiO₂, and therefore the self-formed barrier film 26 is composed of a silicon-containing Mn oxide (MnSi_(x)O_(y)) or Mn oxide (Mn_(x)O_(y)). The film thickness of the self-formed barrier film 26 is 2 nm to 3 nm.

Referring next to FIG. 2K, two-stage polishing is carried out by e.g. CMP. In the first-stage polishing, a MnO layer M (see FIG. 2J) and the part of the conductive layer 25 (see FIG. 2J) unnecessary as an interconnect pattern are removed. Subsequently, in the second-stage polishing, the self-formed barrier film 26 is removed, and the exposed interlayer insulating film 21 is polished down by 100 nm. This results in formation of a via 25 a′ in communication with the interconnect 18′ in the via hole 22 a and formation of an interconnect 25 b′ in the interconnect trench 22 b.

Subsequently, an organic acid cleaning is carried out with use of a citric acid aqueous solution, oxalic acid aqueous solution, and so on, to thereby remove an oxide film on the interconnect 25 b′ and an anticorrosive agent for Cu remaining on the Cu surface after the CMP step. Thereafter, on the interconnect 25 b′ and the interlayer insulating film 21, a cap film 27 composed of e.g. SiCN is deposited to a film thickness of 50 nm.

In this method for manufacturing a semiconductor device, the plating seed layer 24 arising from sequential deposition of the alloy layer 24 a composed of CuMn and the conductive layer 24 b composed of pure Cu is formed as described with FIGS. 2G and 2H. This can offer the same advantages as those by the first embodiment.

In the above-described examples according to the first and second embodiments, the alloy layers 17 a and 24 a are composed of CuMn. Examples of a metal other than Cu contained in the alloy layers 17 a and 24 a include, besides Mn, aluminum (Al), zinc (Zn), chromium (Cr), vanadium (V), titanium (Ti), and tantalum (Ta). For example, when the alloy layers 17 a and 24 a are composed of CuAl, e.g. a silicon-containing Al oxide (AlSi_(x)O_(y)) or Al oxide (Al_(x)O_(y)) is formed as the self-formed barrier film 19. When the alloy layers 17 a and 24 a are composed of CuZn, e.g. a silicon-containing Zn oxide (ZnSi_(x)O_(y)) or Zn oxide (Zn_(x)O_(y)) is formed as the self-formed barrier film 19. Also as for the other metals cited above, a similar silicon compound or oxide is formed.

In the above-described embodiments, a silicon-containing Mn oxide (MnSi_(x)O_(y)) or Mn oxide (Mn_(x)O_(y)) is cited as a Mn compound of the self-formed barrier films 19 and 26. However, if the interlayer insulating films 12, 15, and 21 are formed of an insulating film containing carbon such as an organic insulating film, a Mn carbide (Mn_(x)C_(y)) will be formed as a Mn compound of the self-formed barrier films 19 and 26 in some cases. Furthermore, if the above-described CuAl or CuTi is used as the alloy layer 17 a, an Al carbide (Al_(x)C_(y)) or titanium carbide (Ti_(x)C_(y)) will be formed in some cases. Also as for the other metals cited above, a similar metal carbide is formed.

It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factor in so far as they are within the scope of the appended claims or the equivalents thereof. 

1. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a recess in an insulating film provided over a substrate; forming a plating seed layer in such a way that an inner wall of the recess is covered, the plating seed layer arising from sequential deposition of an alloy layer composed of copper and a metal other than copper and a conductive layer composed mainly of copper; burying a conductive layer composed mainly of copper by plating in the recess on which the plating seed layer is provided; and carrying out heat treatment to cause the metal in the alloy layer to react with a constituent in the insulating film, to thereby form a barrier film composed of a metal compound having a copper diffusion barrier function at an interface between the alloy layer and the insulating film.
 2. The method for manufacturing a semiconductor device according to claim 1, wherein the metal other than copper is manganese and the metal compound is a manganese oxide.
 3. The method for manufacturing a semiconductor device according to claim 1, wherein the metal other than copper is manganese and the metal compound is a silicon-containing manganese oxide. 